1. Field of the Invention
This invention relates to a signal processing device which is arranged to process an information signal.
2. Description of the Related Art
Among known devices of the kind processing information signals, an electronic still video system is arranged to record a still image signal on a magnetic disc and to reproduce the recorded still image signal from the magnetic disc.
The electronic still video system records a color component of the still image signal on the magnetic disc in a state of a color-difference line-sequential signal together with a luminance signal. The color-difference line-sequential signal is formed by line-sequentially processing two color-difference signals (hereinafter referred to as signals R-Y and B-Y).
To draw a distinction between the two color-difference signals R-Y and B-Y, the color-difference line-sequential signal is recorded with a DC offset applied to the signal B-Y in relation to the other signal R-Y. A reproducing apparatus of the electronic still video system, therefore, must be arranged not only to make a discrimination between the signals R-Y and B-Y included in the color-difference line-sequential signal reproduced from the magnetic disc but also to remove the DC offset.
To meet the above-stated requirement, it has been practiced to make a discrimination between the signals R-Y and B-Y included in the color-difference line-sequential signal and to remove the DC offset by means of a signal processing circuit which is arranged as shown in FIG. 1 of the accompanying drawings.
FIG. 1 shows in outline the arrangement of the conventional signal processing circuit. The circuit shown in FIG. 1 is described as follows with reference also to FIGS. 2(a) to 2(e) which show in a timing chart the operation of the circuit. Referring to FIG. 1, the color-difference line-sequential signal (see FIG. 2(a)) is frequency-demodulated by a frequency demodulator (not shown) and is further subject to a deemphasis process at a deemphasis circuit (not shown). The color-difference line sequential signal is then supplied to a terminal PD.
The color-difference line-sequential signal thus inputted to the terminal PD is supplied through a terminal 8c to capacitors C1 and C2 which are arranged as external elements. After the capacitors C1 and C2, the color-difference line-sequential signal is supplied to clamp circuits 1 and 2 through terminals 8a and 8b.
The clamp circuits 1 and 2 operate under the control of control signals RCLP and BCLP which are as shown in FIGS. 2(d) and 2(e). The clamp circuits 1 and 2 are thus arranged to respectively clamp the color-difference line-sequential signal supplied during the high-level periods of the control signals RCLP and BCLP to a reference voltage Vref. The reference voltage Vref is supplied from a reference voltage source 7. A signal outputted from the clamp circuit 1 is supplied to one terminal R of a switch 3. A signal outputted from the other clamp circuit 2 is supplied to the other terminal B of the switch 3.
The switch 3 is arranged to perform a switching action under the control of a switch-over signal LS which is inverted for every horizontal scanning period as shown in FIG. 2(c). For example, the connecting position of the switch 3 is on the side of the terminal B when the level of the switch-over signal LS is high and on the side of the terminal R when the level of the switch-over signal LS is low. As a result of the operation of the switch 3, the color-difference line-sequential signal is outputted from a terminal NOF with the DC offset removed as shown in FIG. 2(b).
The reason for performing the clamping process with the two capacitors and two clamp circuits in the manner described above is as follows: if the clamping process is arranged to be performed with a single capacitor and a single clamp circuit, it is hardly possible to obtain adequate characteristics both for following the DC offset and for holding a potential during each scanning line period at the same time.
The color-difference line-sequential signal inputted to the terminal PD of FIG. 1 is supplied also to sample-and-hold (hereinafter referred to as S/H) circuits 4 and 5. The S/H circuit 4 is arranged to sample the color-difference line-sequential signal during the high-level period of the control signal RCLP and to hold the sampled signal for the low-level period of the control signal RCLP. The other S/H circuit 5 is arranged to sample the color-difference line-sequential signal during the high-level period of the control signal BCLP and to hold the sampled signal for the low-level period of the control signal BCLP.
Capacitors C3 and C4 which are arranged as external elements are connected to the S/H circuits 4 and 5 via terminals 8d and 8e. The capacitors C3 and C4 are provided for the purpose of holding the sampled signals.
With the color-difference line-sequential signal sampled and held in the manner described above, the S/H circuit 4 outputs a voltage signal VDR which indicates the blanking potential of the signal R-Y included in the color-difference line-sequential signal. Meanwhile, the other S/H circuit 5 outputs a voltage signal VDB which indicates the blanking potential of the signal B-Y included in the color-difference line-sequential signal. These voltage signals VDR and VDB are supplied to a comparator 6. The comparator 6 compares the levels of these signals VDR and VDB with each other. The comparator 6 outputs an identification signal CID at a high level if the voltage signal VDR is higher than the voltage signal VDB and at a low level if the voltage signal VDR is lower than the voltage signal VDB.
Further, during the low-level period of the identification signal CID, the operation of the signal processing circuit is in a normal state, which is as follows: The blanking potential of the signal R-Y included in the input color-difference line-sequential signal is sampled and held at the S/H circuit 4. The blanking potential of the signal B-Y is sampled and held at the other S/H circuit 5. Further, the blanking potential of the signal R-Y of the input color-difference line-sequential signal is clamped at the above-stated clamp circuit 1 while the blanking potential of the signal B-Y is clamped at the clamp circuit 2. On the other hand, during the high-level period of the identification signal CID, the operation is in an abnormal state which is as follows: the blanking potential of the signal B-Y included in the input color-difference line-sequential signal is sampled and held at the S/H circuit 4, and that of the signal R-Y is sampled and held at the S/H circuit 5. Further, the blanking potential of the signal B-Y of the input color-difference line-sequential signal is clamped at the clamp circuit 1 while that of the other signal R-Y is clamped at the clamp circuit 2.
Therefore, in a case where the identification signal CID is at a high level thus indicating an abnormal state, the signal processing circuit is brought back to the normal operating state by a switching action which is performed in such a way as to supply the control signal BCLP to the clamp circuit 1 and the S/H circuit 4 and to supply the control signal RCLP to the clamp circuit 2 and the S/H circuit 5.
In accordance with the arrangement of the conventional signal processing device described above, the four capacitors Cl to C4 must be arranged as external elements (to be attached to the outside of the circuit). Therefore, in order to arrange the signal processing device in the form of an integrated circuit, the circuit must be provided with a total of five external-element connecting terminals for connecting the capacitors Cl to C4. In arranging the integrated circuit, however, it is advantageous to minimize the number of external-element connecting terminals in respect to reduction in size and weight. In other words, use of many elements attached to the outside of the integrated circuit not only increases a space required for assembling the circuit into the device but also increases the weight of the device.
Besides, the possibility of malfunction due to inadequate contact increases accordingly as the number of external-element connecting terminals increases. It is, therefore, preferable to minimize the number of such terminals.